Delay line is a device where an input signal reaches the output of the device after a known period of time has elapsed. Delay lines are used to derive precise delay in various electronic devices based on control parameters such as voltage and current. Based on control parameters, two types of delay lines are commonly known, Voltage Controlled Delay Line (VCDL) and Current Controlled Delay line (CCDL). The delay lines are critical functional blocks in Phase-locked loops (PLLs) and Delay-locked loops (DLLs). Delay lines also find applications in programmable devices such as Field Programmable Gate Array (FPGA) and Complex Programmable Logic Device (CPLD). Another application of delay line is in digital direct synthesis (DDS) to reduce time jitter of the signal by using virtual clock enhancement method.
A typical delay line includes multiple delay elements. The delay element is the basic component that generates delay in a delay line. Two commonly used delay elements are CMOS delay elements and differential delay elements. A very basic example of CMOS delay element is a CMOS inverter. Each of the delay element in the delay line is configured to produce a finite delay. However, delay at any chosen tap in a delay line vary over a relatively large range due to variations in operating conditions such as effects of temperature, supply voltage, and device parameter variations. The delay varies in a delay element due to bias current variation and load capacitance variation across process, temperature and supply variations. The process variation is defined in terms of variations in gate oxide thickness, doping concentration and geometry of the delay element. The process variations change the threshold voltage and mobility of the delay element. As a result, delay varies across multiple process corners in a delay line.
Various conventional methods have been used to achieve better delay accuracy and minimize delay variation. One such method employs closed loop feedback around the delay line for PVT compensation at the cost of power in milliwatts. The delay variation is minimized by using feedback in the form of phase or delay locked loop to adjust the delay by tracking the period of a reference clock. Other methods facilitate coarse delay tuning by choosing appropriate delay element and then varying control parameter for fine tuning. However, these schemes require closed loop architecture of delay line, resulting in extra hardware overhead and high current requirement. Therefore, the closed loop architecture is not suitable for low power applications. The method and system of the present invention enable low power open loop compensation of delay variations in a delay line.